With the ever-growing needs for wireless communications, more efforts have been made to provide a fully integrated radio frequency (RF) transceiver, which would result in lower bill of materials, a smaller form factor, and more functionality. A complementary metal oxide semiconductor (CMOS) power amplifier (PA) may be a good candidate to achieve one or more of the foregoing goals, and a higher level of transceiver integration that includes a PA has recently been demonstrated for some wireless communications such as wireless LAN, Bluetooth, and Cordless phone. However, CMOS PAs need to utilize various techniques such as a distributed active-transformer, Doherty, parallel power combining, and polar transmission to compete with HBT PAs, because the power capability of CMOS transistors is much less than that of hetero junction bipolar transistor (HBT) PAs. With continuous research to improve power and efficiency, switching CMOS PAs have attracted attention for their high power-added efficiency (PAE), but at the sacrifice of linearity. For a linear CMOS PA, however, good linearity and good efficiency cannot be easily achieved at the same time. Since recent wireless systems require a high peak-to-average ratio (PAPR) to increase data rates, linear PAs should operate at a power back-off of a PAPR from 1 dB power compression point (P1dB), which results in a heavy loss of PAE.